计算机工程与应用2011，Vol.47Issue(35)：81-83,87,4.DOI:10.3778/j.issn.1002-8331.2011.35.023
5.2GHzCMOS功率放大器设计
Design of 5.2 GHz power amplifier implementation in CMOS technology
刘高辉 1马晓波1
作者信息
- 1. 西安理工大学自动化与信息工程学院,西安710048
- 折叠
摘要
Abstract
WLAN power amplifier of two-stage differential structure is designed for 5.2 GHz, which adopts TSMC 0.18 urn CMOS technology.In order to improve its linearity and power added efficiency, inductors are introduced between each differ ential amplifier stage Cascode circuit, and some series-parallel MOS transistors are introduced at every level within the Cas code amplifiers.By using ADS2009 and Cadence software, the layout of the power amplifier circuits are drawn that have been completing design and simulation.The simulation shows that under the 1.8 V working voltage,the output power is 19.6 dBm, the power gain is 28.2 dB.the PAE is 18.1% in the 1 dB compression point.lt can be adopted in the wireless LAN 802.11a standard systems.关键词
CMOS/无线局域网/功率放大器/版图Key words
CMOS/ Wireless Local Area Networks (WLAN)/ power amplifier/ layout分类
信息技术与安全科学引用本文复制引用
刘高辉,马晓波..5.2GHzCMOS功率放大器设计[J].计算机工程与应用,2011,47(35):81-83,87,4.
