山东科学2011，Vol.24Issue(5)：22-25,4.
基于射极耦合逻辑的数字延迟系统
An emitter coupled logic based digital delay system
王忠民 1赵鑫 1王丰贵 1张延波 1杨传法 1张琳1
作者信息
- 1. 山东省科学院自动化研究所,山东济南250014
- 折叠
摘要
Abstract
This paper presented a novel digital delay system based on such positives as high conversion rate, low delay and high reliability of emitter coupled logic （ECL）. The LVTTL signal ,which was the output of FPGA and served as the input trigger signal, was transmitted to AD9500 after level conversion. The delayed output signal of AD9500 was converted back to LVTTL signal to be the ouput signal of the system terminal. Differential signal served as the input of the system, and terminal circuit was employed to process the transmitted signal. Test results show that the system achieves a delay resolution of 100 ps.关键词
数字延迟/射极耦合逻辑/AD9500Key words
digital delay/emitter coupled logic/AD9500分类
信息技术与安全科学引用本文复制引用
王忠民,赵鑫,王丰贵,张延波,杨传法,张琳..基于射极耦合逻辑的数字延迟系统[J].山东科学,2011,24(5):22-25,4.
