无线电工程2012，Vol.42Issue(2)：55-57,64,4.
准循环LDPC码的部分并行译码算法
Partly Parallel DecodingAlgorithm of Quasi-cyclic LDPC Codes
赵建功 1刘香玲2
作者信息
- 1. 中国电子科技集团公司第五十四研究所,河北石家庄050081
- 2. 石家庄铁道大学电气与电子工程学院,河北石家庄050043
- 折叠
摘要
Abstract
The quasi-cyclic low density parity check codes（LDPC） defined in IEEE802.16e standard is a kind of nonlinear block codes.A normalized min-sum（NMS） algorithm based on partly parallel structure is studied aiming at the sparse and quasi-cyclic characteristics of parity-check matrix of LDPC codes.The methods for quantizing and exchanging the decoding messages are given.The Performance of decoding algorithm in Gaussian channel is verified by numerical simulation.The decoding algorithm is implemented by Field Programmable Gate Arrays（FPGA）.关键词
纠错码/低密度奇偶校验码/归一化最小和算法/准循环Key words
error-correction codes/low-density parity-check codes/normalized min-sum algorithm/quasi-cyclic分类
信息技术与安全科学引用本文复制引用
赵建功,刘香玲..准循环LDPC码的部分并行译码算法[J].无线电工程,2012,42(2):55-57,64,4.
