微型机与应用2011，Vol.30Issue(20)：30-32,3.
一种13bit40MS／s采样保持电路设计
Design of a 13 bit 40 MS/s sample-and-hold circuit
摘要
Abstract
A 13 bit 40 MS/s sample-and-hold circuit for the pipelined A/D converters is designed. Capacitor flip-around ar- chitecture and gain-boosting folded cascade operational transconductance amplifier are adopted to achieve high resolution and resolu- tion. In order to reduce the nonlinearity related to input signal, a bootstrapped switch is used. The S/H circuit is designed and simulated in TSMC＇s 0. 18 μm CMOS process at 3.3V supply voltage. Simulation results show that SNDR of 84.8dB and SFDR of 92 dB are achieved at 40 MHz sampling rate.关键词
采样保持电路/电容翻转结构/增益提高/栅压自举开关Key words
Sample and hold circuit/capacitor flip-around architecture/gain-boosting/bootstrapped switch分类
信息技术与安全科学引用本文复制引用
杨骁,刘杰,齐骋,凌朝东..一种13bit40MS／s采样保持电路设计[J].微型机与应用,2011,30(20):30-32,3.基金项目
福建省自然科学基金 （）
华侨大学基本科研业务费譬项基金 （）
