现代电子技术2011，Vol.34Issue(22)：158-161,4.
YUV分离的两种FPGA实现
Two Implementation Methods of YUV Separation Based on FPGA
耿宏伟 1张玉璘1
作者信息
- 1. 济南大学信息科学与工程学院,山东济南250022
- 折叠
摘要
Abstract
The transform of speed and area is a eternal issue in the design based on FPGA. Two implementation methods (respectively based on area and speed) of YUV separation based on FPGA are introduced in this paper. The former achieves the separation data output of YUV with only a dual-port RAM, and the later fulfills the design of whole module with ping-pong operation between two dual-port RAMs by the way of pipeline. Both the two ways are implemented with Verilog HDL, and the module simulation is achieved with ModelSim. It is found by comparison that both of the two designs have their own superiorities:the former saves the hardware resources greatly, and the later improves the real-time performance of the whole system significantly. Both the two methods offer the workable measures to settle YUV separation in different views.关键词
FPGA/YUV分离/双口RAM/流水线Key words
FPGA/YUV separation/dual-port RAM/pipleline/ping-pong operation分类
信息技术与安全科学引用本文复制引用
耿宏伟,张玉璘..YUV分离的两种FPGA实现[J].现代电子技术,2011,34(22):158-161,4.
