现代电子技术2012，Vol.35Issue(2)：165-167,3.
一种低压高频CMOS电流乘法器的设计
Design of low-voltage high-frequency CMOS current multiplier
摘要
Abstract
A new high-frequency four-quadrant current multiplier is presented. The current multiplier uses complementary MOS devices working in triode region and adopts the squarelaw characteristic of saturated MOS transistor. The circuit employs 0. 35μm technique of CMOS. The results of HSPICE simulation show that the proposed multiplier has a static-state power dissipation of 1. 18 Mw and the cut-off frequency is 1. 741 GHz when multiplier circuit works at the supply voltage of ± 1.18 V. Compared with the previous current multiplier circuits, this multiplier circuit can work at lower voltage and higher frequency.关键词
CMOS电流乘法器/低压/高频/电流减法器Key words
CMOS current multiplier/ low-voltage/ high-frquency/ current subtractor分类
信息技术与安全科学引用本文复制引用
解鸿国..一种低压高频CMOS电流乘法器的设计[J].现代电子技术,2012,35(2):165-167,3.基金项目
国家自然科学基金项目(61061006) （61061006）
广西研究生教育创新计划资助项目(2010106020809M50) （2010106020809M50）
