基于FPGA的EoS系统中帧处理的改进与实现OA北大核心CSCDCSTPCD
Improvements and implementation of frame processing in EoS system based on FPGA
根据ITU-T X.86协议的规定,设计了一种EoS系统,实现了IP数据包在基于SDH的骨干光传输网络中的高速传输.针对现有帧处理方案在帧同步时延和时钟抖动方面存在的问题,提出了改进的快速帧同步机制和时钟提取方案.采用廉价的FPGA硬件编程实现,通过电路综合与时序仿真表明,方案在缩短帧同步时延和消除时钟抖动方面具有较好的效果.
According to the provisions of the ITU-T X.86 agreements EoS system has been designed and achieved the high-speed transmission of IP packet in the SDH-based backbone optical transmission network. Frame synchronization delay and clock jitter are existing in the current frame processing program,for the problems,a improved rapid frame synchronization mechanism and clock extraction scheme have been presented. With cheap FPGA hardware programming,circuits integra…查看全部>>
彭煜;黄红斌;刘伟平;陈舜儿
暨南大学电子工程系,广州510632暨南大学光电信息与传感技术广东普通高校重点实验室,广州510632暨南大学电子工程系,广州510632暨南大学光电信息与传感技术广东普通高校重点实验室,广州510632
信息技术与安全科学
EoS快速帧同步时钟同步FPGA
fast frame synchronization clock synchronization FPGA
《光通信技术》 2012 (3)
10-13,4
广东省教育部产学研结合项目(2009B090200023)资助国家973计划项目(2010CB327806)资助.
评论