计算机工程2012，Vol.38Issue(6)：244-246,3.DOI:10.3969/j.issn.1000-3428.2012.06.081
基于FPGA的SM3算法优化设计与实现
Optimization Design and Implementation of SM3 Algorithm Based on FPGA
摘要
Abstract
Aiming at SM3 cryptographic Hash algorithm released by state cryptography administration, the general working flow of the algorithm is summarized in this paper. Based on Field Programmable Gate Array(FPGA) platform, the IP architecture of the SM3 is proposed, and the optimization design of its relevant crucial path is discussed. Choosing three Cyclone FPGAs of Altera corporation as the target devices, the fast implementation of the SM3 is achieved and is compared with some other existing research fruits. Comparison results indicate that the IP implementation of the SM3 consumes smaller logic element and memory bit but has higher algorithm performance. It can provide the algorithm engine for the development of cryptography System on Chip(SoC) products in practice.关键词
密码杂凑算法/片上系统/关键路径/IP核/现场可编程门阵列Key words
cryptographic Hash algorithm/ System on Chip(SoC)/ crucial path/ IP core/ Field Programmable Gate Array(FPGA)分类
信息技术与安全科学引用本文复制引用
王晓燕,杨先文..基于FPGA的SM3算法优化设计与实现[J].计算机工程,2012,38(6):244-246,3.基金项目
现代通信国家重点实验室基金资助项目(9140C1106021006) （9140C1106021006）
郑州市科技创新型科技人才队伍建设工程基金资助项目(096SYJH21099) （096SYJH21099）
