计算机技术与发展2012，Vol.22Issue(2)：103-106,4.
基于FPGA可扩展的Mapreduce架构设计与实现
Scalable Mapreduce Framework Design and Realization Based on FPGA
摘要
Abstract
It presents a scalable Mapreduce framework on FPGA to accelerate commodity hardware. In this design,commodity hardware (CH) runs the main framework to communicate with file system in networks, while FPGA based platform is linked with CH to run Mapreduce tasks. Due to resource limited in one chip,more tasks can be extended to more FPGA platforms to achieve high-speed performance. A virtual device driver is designed in software to manage tasks running in special hardware. According to internal pipeline design and scalability, the design is proved that it allows better performance than commodity hardware, and also provides advantages in scalability and flexibility.关键词
Mapreduce架构/FPGA/可扩展/协处理系统/流水线操作Key words
Mapreduce framework/FPGA/scalable/coprocessor system/pipeline分类
信息技术与安全科学引用本文复制引用
李绍松,尹栋,慕德俊,戴冠中..基于FPGA可扩展的Mapreduce架构设计与实现[J].计算机技术与发展,2012,22(2):103-106,4.基金项目
:北工业大学研究生创业种子基金(Z2011049) （Z2011049）
