计算机技术与发展2012，Vol.22Issue(3)：149-152,156,5.
基于FPGA的智能误码测试仪
IntelligentBit Error Rate Tester Based on FPGA
摘要
Abstract
Most of the existing commercial bit error rate tester ( BERT) can not be completed on the actual work in the special channel for bit error test. BERT is presented based on FPGA chip, which is designed with multi-interface code patterns and multi-transmission rates, starting from the basic block graph of the error code instrument. Introduce the function of each module, then lay emphasis on discussion of the implementation method for the key module in the error code instrument. On this basis,also present a new statistical method to achieve error rate, avoiding insignificant division calculation and instead of less resource consumption to achieve bit error rate. BERT selected the single chip computer and the FPGA device for upgrading and improving its probability.关键词
FPGA/m序列/HDB3编译码/位同步/误码率Key words
FPGA/m arrange/HDB3 code and decode/bit synchronization/BER分类
信息技术与安全科学引用本文复制引用
唐维智,刘瑞兰..基于FPGA的智能误码测试仪[J].计算机技术与发展,2012,22(3):149-152,156,5.基金项目
南京邮电大学基金(NY207507) （NY207507）
