西北师范大学学报（自然科学版）2012，Vol.48Issue(1)：48-51,4.
基于FPGA的高速全并行FIR滤波器的设计
The design of parallel high-speed FIR filter based on FPGA
摘要
Abstract
A parallel high-speed pipelined FIR filter implemented in FPGA is presented. The filter tap coefficients are generated by MATLAB using windowing method. The hardware parallel structure diagram is got from linear phase direct form FIR filter structure. The filter coefficients of the multiplier is fixed as a constant, rather than read from the ROM. The inserted registers after the adders and multipliers constitute a multi-stage pipeline structure. The 128-tap linear phase FIR filter is implemented in FPGA by using verilog HDL RTL-level description. The performance of the filter is analyzed with the network analyzer machine. One point computing result is completed in single clock.关键词
FPGA/FIR滤波器/流水线/并行结构Key words
FPGA/ FIR filter/ pipeline/ parallel architecture分类
信息技术与安全科学引用本文复制引用
杨鸿武,丁朋程,王全州..基于FPGA的高速全并行FIR滤波器的设计[J].西北师范大学学报（自然科学版）,2012,48(1):48-51,4.基金项目
国家自然科学基金资助项目(60875015) （60875015）
甘肃省自然科学基金资助项目(1107RJZA112) （1107RJZA112）
