信息与电子工程2012，Vol.10Issue(1)：107-109,117,4.
并行化改进遗传算法的FPGA高速实现方法
Methodology of realizing FPGA for improved parallel genetic algorithm
摘要
Abstract
To enhance the operation speed and utilize the resource, according to the idea of hardware parallel method, one traditional implementation of genetic algorithms is improved by separating controlling part into other components and using Field Programmable Gate Array(FPGA) to realize control in pipelining mode. The result of synthesis shows its frequency can reach 137.08 MHz for evolution of a generation needing 64 cycles(namely 0.467 μs). With optimized hardware resources and high efficiency, the realized structure demonstrates the possibility of large-scale and high-speed hardware realization of genetic algorithms.关键词
遗传算法/硬件并行化/现场可编程逻辑门阵列/演化Key words
genetic algorithms/hardware parallel/Field Programmable Gate Array/evolution分类
信息技术与安全科学引用本文复制引用
张妮娜,窦衡..并行化改进遗传算法的FPGA高速实现方法[J].信息与电子工程,2012,10(1):107-109,117,4.基金项目
国家自然科学基金资助项目(61001032/F010501) （61001032/F010501）
