半导体学报2012，Vol.33Issue(3)：114-117,4.DOI:10.1088/1674-4926/33/3/036001
Metal gate etch-back planarization technology
Metal gate etch-back planarization technology
摘要
Abstract
Planarization used in a gate-last CMOS device was successfully developed by particular technologies of SOG two-step plasma etch-back plus one special etch-back step for SOG/SiO2 interface trimming.The within-thewafer ILD thickness non-uniformity can reach 4.19％ with a wafer edge exclusion of 5 mm.SEM results indicated that there was little “dish effect” on the 0.4 μm gate-stack structure and finally achieved a good planarization profile on the whole substrate.The technology provided a CMP-less process basis for sub-100 nm high-k/metal gate-last CMOS integration.关键词
metal gate/plasma etch-back/planarization/spin on glassKey words
metal gate/plasma etch-back/planarization/spin on glass引用本文复制引用
Meng Lingkuan,Yin Huaxiang,Chen Dapeng,Ye Tianchun..Metal gate etch-back planarization technology[J].半导体学报,2012,33(3):114-117,4.基金项目
Project supported by the Chinese National Science and Technology Major Project (No.2009ZX02035),the Special Funds for Major State Basic Research Projects,China (No.2006CB302704),and the Opening Project of Key Laboratory of Microelectronics Devices of Integrated Technology (IMECAS). （No.2009ZX02035）
