电子科技2012，Vol.25Issue(5)：108-110,114,4.
基于Virtex-4的DCM动态重配置设计
DCM Dynamic Reconfiguration Design Based on Virtex-4
方火能 1邢开宇 1曹晓曼1
作者信息
- 1. 西安电子科技大学电子工程学院,陕西西安710071
- 折叠
摘要
Abstract
This paper introduces the structure and related characteristics of Digital Clock Manager（DCM） in Xilinx FPGA,proposes a scheme reconfiguring the DCM dynamically based on Xilinx FPGA,and gives the specific implementation system.With just a few external control signal lines connected to Xilinx XC4VFX100,this system can enable DCM to change frequency accurately and quickly between 50 MHz and 300 MHz under the 100 MHz input clock source conditions.This design system features a simple interface,real time and high stability,and has already been applied to some satellite system successfully.关键词
DCM动态重配置/Xilinx/Virtex-4/时钟源Key words
DCM dynamic reconfiguration ports/Xilinx Virtex-4/clock source分类
信息技术与安全科学引用本文复制引用
方火能,邢开宇,曹晓曼..基于Virtex-4的DCM动态重配置设计[J].电子科技,2012,25(5):108-110,114,4.
