可编程FIR滤波器的FPGA实现OA北大核心CSTPCD
The Realization of Programmable FIR Filter on FPGA
介绍了FIR滤波器的基本的线性相位结构及FIR滤波器的抽头系数SD算法编码.给定滤波器的数字指标,用MATLB设计抽头系数,最后用Verilog HDL语言实现了一个16阶的FIR低通滤波器并在QuartusⅡ上仿真,并对仿真结果与理论值进行比较,波形仿真结果和理论值相吻和,最后将编程数据文件下载到FPGA芯片上.对于不同性能的FIR滤波器,抽头系数是变化的,因此只要对本设计的抽头系数重新在线配置,就可以实现不同的FIR滤波器.
The paper introduced an architecture of linear phase FIR filter and SD coding algorithm of FIR filter coef-ficients, gave a digital filter index,and then tap coefficients were gained by MATLAB,finally the 16 order low-pass filter was achieved by using Verilog HDL language and simulating on Quartus ? . The results of waveform simulation and the theoretical value met each other by making a comparison between them. And the programming data files are downloaded …查看全部>>
谢海霞;孙志雄
琼州学院电子信息工程学院,海南三亚572022琼州学院电子信息工程学院,海南三亚572022
信息技术与安全科学
FIR滤波器FPGAQuartusⅡVerilog HDL
FIR filterFPGAQuartus Ⅱ Verilog HDL
《电子器件》 2012 (2)
232-235,4
海南省自然科学基金项目(611133)三亚市院地科技合作项目(2010YD33)三亚市院地科技合作项目(2011YD03)
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