哈尔滨工程大学学报2012，Vol.33Issue(2)：226-233,8.DOI:10.3969/j.issn.1006-7043.201104005
可重构处理器的AVS高清解码探究
Research of audio video standard (AVS) HD decoding based on a reconfigurable processor
摘要
Abstract
According to key technologies of embedded high-performance parallel computing for a new reconfigurable processor architecture, dynamic configuration, multi-task scheduling, and operational management, a new method of AVS HD decoding implementation was proposed in this paper. The decoding process was based on a reconfigurable system known as Remus ( reconfigurable multimedia system). By mapping the algorithms of AVS to Remus, the system could support 1080p (30 f/s) real-time decoding of the AVS JiZhun profile at 200 MHz; this was proven by simulation. The reconfigurable technology based decoding system is much more flexible than the existing system and is mostly based on the application specific integrated circuit ( ASIC) , with an even higher-level performance of acceleration than the existing hardware accelerator, especially in cyclic computing.关键词
可重构处理器/AVS/高清/REMUS/视频解码Key words
reconfigurable processor/ AVS/ HD/ REMUS/ video decoding分类
信息技术与安全科学引用本文复制引用
赵静,周莉,喻庆东,陈杰..可重构处理器的AVS高清解码探究[J].哈尔滨工程大学学报,2012,33(2):226-233,8.基金项目
国家863计划资助项目(2009AA011700). （2009AA011700）
