计算机工程与科学2012，Vol.34Issue(5)：73-77,5.DOI:10.3969/j.issn.1007-130X.2012.05.015
一种低功耗异步乘法器的研究与实现
Research and Implementation of a Low Power Asynchronous Multiplier
摘要
Abstract
The asynchronous logic only performs actions on demand, and it is often adopted in the power-efficient design. There are three significant factors that may affect the power consumption of pipelined circuits: the structure of the pipeline, the behavior of the operation, and characteristics of operands. In this paper, the three factors are analyzed, and a power-optimized de-synchronized multiplier considering the influence of the factors is designed. The experiments show that the proposed multiplier has lower power dissipation and higher performance than the traditional de-synchronized multipliers.关键词
异步/流水线结构优化/操作数检测/低功耗/乘法器Key words
asynchronous/pipeline structure optimization/operand detectingslow power/multiplier分类
信息技术与安全科学引用本文复制引用
石伟,苏博,任洪广,王志英..一种低功耗异步乘法器的研究与实现[J].计算机工程与科学,2012,34(5):73-77,5.基金项目
国家863计划资助项目(2007AA01Z101) （2007AA01Z101）
国家自然科学基金资助(60873015) （60873015）
