计算机与数字工程2012，Vol.40Issue(5)：130-132,3.
基于FPGA的除法器设计
Design of Divider Based on FPGA
摘要
Abstract
Divider is not only the most common, but also the most complex component in digital signal domain. It's used to use the iterative algorithm to implement it, and has lower real-time. To improve the real-time,this paper introduces a design of the digital complex divider which based on linear approximation algorithm and ROM look-up table. Compared to the traditional method, it not only has the less resource and the fast speed, but also can meet more flexible performance requirement with modifying the data precision stored in the ROM, so it has a widely application in digital signal process domain.关键词
FPGA/除法器/线性逼近/查找表Key words
FPGA/ divider/ linear approximation/ look-up table分类
信息技术与安全科学引用本文复制引用
罗瑜,王钟斐,贾晓云..基于FPGA的除法器设计[J].计算机与数字工程,2012,40(5):130-132,3.基金项目
陕西省教育厅科技计划项目(编号:2010kg432)资助. （编号:2010kg432）
