物理学报2012，Vol.61Issue(6)：453-459,7.
一种考虑硅通孔电阻-电容效应的三维互连线模型
Through-silicon-via-aware interconnect prediction model for 3D integrated circuirt
摘要
Abstract
Through-silicon-via（TSV） is one of the major design techniques in three- dimensional integrated circuit（3D IC）.Based on the parasitic parameter extraction model,the parasitic resistance-capacitance（RC） parameters for different size TSVs are acquired and validated with Q3D simulation data.Using the results of this model,closed-form delay and power consumption expressions for buffered interconnect used in 3D IC are presented.Comparative results with 3D net without TSV in various cases show that TSV RC effect has a huge influence on delay and power of 3D IC,which leads maximum delay and power comsumption to extra increase 10% and 21%on average,respectively.It is crucial to correctly establish a TSV-aware 3D interconnect model in 3D IC front-end design.关键词
三维集成/硅通孔/互连延时/功耗Key words
3D integrated circuit/TSV/interconnect delay/power consumption分类
信息技术与安全科学引用本文复制引用
钱利波,朱樟明,杨银堂..一种考虑硅通孔电阻-电容效应的三维互连线模型[J].物理学报,2012,61(6):453-459,7.基金项目
国家自然科学基金 （）
国家科技重大专项（批准号：2009ZX01034-002-001-005）资助的课题 （）
