微型机与应用2012，Vol.31Issue(5)：54-56,3.
混合型判决反馈均衡器设计与FPGA实现
Design and FPGA implementation of decision feedback equalizer of hybrid architecture
杨滔 1宋学瑞 1曹宏徙1
作者信息
- 1. 中南大学信息科学与工程学院,湖南长沙410004
- 折叠
摘要
Abstract
This paper compares several architectures according to SNR and bit error ratio, speed and hardware cost. A hybrid architecture is proposed which meets the speed and bit error requirements and has lower hardware cost. It removes the less significant ISI by a pre-equalizer, and applies pipelining and retiming technologies to improve its performance.关键词
判决反馈均衡/1000BASE—T/混合结构/网格译码Key words
decision feedback equalizer/1000BASE-T/hybrid architecture/trellis decoding分类
信息技术与安全科学引用本文复制引用
杨滔,宋学瑞,曹宏徙..混合型判决反馈均衡器设计与FPGA实现[J].微型机与应用,2012,31(5):54-56,3.
