现代电子技术2012，Vol.35Issue(7)：69-72,76,5.
基于FPGA的高速实时数据采集系统设计
Design of high speed real-time data acquisition system based on FPGA
张秋云 1王黎 1高晓蓉 1王泽勇 1郭建强1
作者信息
- 1. 西南交通大学光电工程研究所,四川成都610031
- 折叠
摘要
Abstract
A high speed real-time data acquisition system based on FPGA is designed. The process of system is that six o-riginal analog signals are collected and processed, and stored in the FIFOs memories in the FPGA, then shifted to the DSP for real-time processing through the data bus, finally uploaded to the host display. The procedure is programed with Verilog HDL language and simulated with Quartus II and other EDA software in order to verify the correctness of the design. Satisfactory results have been obtained.关键词
FPGA/Verilog HDL/FIFO/数据采集Key words
FPGA/Verilog HDL/FIFO/data acquisition分类
信息技术与安全科学引用本文复制引用
张秋云,王黎,高晓蓉,王泽勇,郭建强..基于FPGA的高速实时数据采集系统设计[J].现代电子技术,2012,35(7):69-72,76,5.
