现代电子技术2012，Vol.35Issue(10)：43-46,4.
基于Verilog HDL语言的CAN总线控制器设计及验证
Design and confirmation of CAN bus controller based on Verilog HDL
许莉娅 1段帅君 2李传南2
作者信息
- 1. 黎明职业大学机电工程系,福建 泉州 362000
- 2. 吉林大学电子科学与工程学院,吉林长春 130012
- 折叠
摘要
Abstract
One type of CAN bus controller was designed with Verilog HDL and tested by the aid of a Cyclone FPGA chip. This CAN bus controller was divided into three functional modules: interface management logic module, register module and CAN core module. Every module was designed with Verilog HDL according to their functions. The functions of these modules were simulated by means of the software Modelsim. The CAN bus controller was verified by FPGA chip, and tested together with a four-node CAN network. The testing results show that the CAN bus controller can implement the required functions.关键词
CAN总线/控制器/FPGA/Verilog HDLKey words
CAN bus/ controller/ FPGA/ Verilog HDL分类
信息技术与安全科学引用本文复制引用
许莉娅,段帅君,李传南..基于Verilog HDL语言的CAN总线控制器设计及验证[J].现代电子技术,2012,35(10):43-46,4.
