现代电子技术2012，Vol.35Issue(10)：90-92,96,4.
基于FPGA的H.264DCT算法的硬件实现
Implementation of FPGA-based hardware of H.264 DCT algorithm
刘斌 1何剑锋 1孙玲玲1
作者信息
- 1. 杭州电子科技大学 射频电路与系统教育部重点实验室,浙江杭州 310018
- 折叠
摘要
Abstract
Two-dimensional DCT hears the function of signal transform from the time domain to frequency domain in the H. 264 video coding. An efficient H. 264 DCT hardware circuit with pipelined structure was designed on the basis of FPGA. The two-dimensional 4X4 DCT is transformed into a second-order one-dimensional DCT (whose butterfly algorithm is familier anyway). Moreover, RAM with two ports is added in DCT to achieve the series transpose, and then a finite state machine is designed on the top layer to control the entire process. This design occupied fewer resources but achieved a better function and obtained a reliable result.关键词
二维离散余弦变换/FPGA/H.264/DCTKey words
two-dimensional discrete cosine transformj FPGA/ H. 264/ DCT分类
信息技术与安全科学引用本文复制引用
刘斌,何剑锋,孙玲玲..基于FPGA的H.264DCT算法的硬件实现[J].现代电子技术,2012,35(10):90-92,96,4.
