现代电子技术2012，Vol.35Issue(11)：23-26,4.
基于Wishbone和端点IP的PCIE接口设计
Design of PCIE interface based on Wishbone and endpoint IP
罗宣平 1刘本源 1卢再奇1
作者信息
- 1. 国防科学技术大学ATR国家重点实验室,湖南长沙410073
- 折叠
摘要
Abstract
The FPGA-embedded PCI Express hardcore endpoint module and specification for Wishbone bus-on-chip are introduced. VHDL language was adopted for programming to realize the master-slave port of Wishbone bus and code-decode function of TLP packet. The program is runned on FPGA and the time-sequence waveform is tested by Chipscope. The stabilization and accurateness of the data transmission through the port were verified.关键词
PCI Express总线/FPGA/PCIE端点模块/WishboneKey words
PCI Express bus/FPGA/PCI Express endpoint module/Wishbone分类
信息技术与安全科学引用本文复制引用
罗宣平,刘本源,卢再奇..基于Wishbone和端点IP的PCIE接口设计[J].现代电子技术,2012,35(11):23-26,4.
