电子科技2012，Vol.25Issue(6)：110-114,5.
通用数字电路板测试系统硬件设计
Hardware Design of a General Digital Circuit Board Testing System
周博 1刘文波1
作者信息
- 1. 南京航空航天大学自动化学院,江苏南京210016
- 折叠
摘要
Abstract
The conventional method of using an oscilloscope, muhimeter, logic analyzer or other equipment for digital circuit board testing is complex, time consuming and not reliable. In this paper, the hardware design of a general digital circuit board testing system is introduced. Unlike traditional digital circuit board testing systems, this design has better performance and parameters： the testing frequency can reach 50 MHz and can be set as integer di- vision of 100 MHz; the testing level is compatible to -6 V - ＋ 9 V and can be programmed by 100 mV ; there are up to 32 channels, each channel having 1 Mbit memory depth and 50 mA current drive capability with overload pro- tection, and can work either as input or output for three-state synchronously.关键词
数字电路板测试/嵌入式硬件设计/FPGAKey words
digital circuit board testing/embedded hardware design/FPGA分类
信息技术与安全科学引用本文复制引用
周博,刘文波..通用数字电路板测试系统硬件设计[J].电子科技,2012,25(6):110-114,5.
