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A fast combination calibration of foreground and background for pipelined ADCs

Sun Kexu He Lenian

半导体学报(英文版)2012,Vol.33Issue(6):84-94,11.
半导体学报(英文版)2012,Vol.33Issue(6):84-94,11.DOI:10.1088/1674-4926/33/6/065007

A fast combination calibration of foreground and background for pipelined ADCs

A fast combination calibration of foreground and background for pipelined ADCs

Sun Kexu 1He Lenian1

作者信息

  • 1. Institute of VLSI Design,Zhejiang University,Hangzhou 310027,China
  • 折叠

摘要

Abstract

This paper describes a fast digital calibration scheme for pipelined analog-to-digital converters (ADCs).The proposed method corrects the nonlinearity caused by finite opamp gain and capacitor mismatch in multiplying digital-to-analog converters (MDACs).The considered calibration technique takes the advantages of both foreground and background calibration schemes.In this combination calibration algorithm,a novel parallel background calibration with signal-shifted correlation is proposed,and its calibration cycle is very short.The details of this technique are described in the example of a 14-bit 100 Msample/s pipelined ADC.The high convergence speed of this background calibration is achieved by three means.First,a modified 1.5-bit stage is proposed in order to allow the injection of a large pseudo-random dithering without missing code.Second,before correlating the signal,it is shifted according to the input signal so that the correlation error converges quickly.Finally,the front pipeline stages are calibrated simultaneously rather than stage by stage to reduce the calibration tracking constants.Simulation results confirm that the combination calibration has a fast startup process and a short background calibration cycle of 2×221 conversions.

关键词

background calibration/capacitor mismatch and gain calibration/digital calibration/foreground calibration/pipelined analog-to-digital converter/signal-shifted correlation

Key words

background calibration/capacitor mismatch and gain calibration/digital calibration/foreground calibration/pipelined analog-to-digital converter/signal-shifted correlation

引用本文复制引用

Sun Kexu,He Lenian..A fast combination calibration of foreground and background for pipelined ADCs[J].半导体学报(英文版),2012,33(6):84-94,11.

基金项目

Project supported by the National Key Project,China (No.2008zx010200001). (No.2008zx010200001)

半导体学报(英文版)

OACSCDCSTPCDEI

1674-4926

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