微型机与应用2012，Vol.31Issue(13)：87-89,92,4.
FSATA乘法器的设计与实现
Design and implementation of FSATA multiplier
摘要
Abstract
In order to improve the computing speed, reduce the delay of the array multiplier, a design based on four-to-one multiplexer was proposed. Two bits of the multiplier were executed on every step, so that the number of all partial products was reduced to half. Eventually, the FSATA multiplier was encoded by VHDL. The synthesis and simulation result in Quartus showed that the FSATA multiplier has a better performance.关键词
阵列乘法器/FSATA乘法器/多路选择器/VHDL/QuartusKey words
array multiplier/FSATA multiplier/multiplexer/VHDL/Quartus分类
计算机与自动化引用本文复制引用
商丽卫,刘耀军..FSATA乘法器的设计与实现[J].微型机与应用,2012,31(13):87-89,92,4.基金项目
基金项目：山西省重点学科专项基金项目 （）
