FSATA乘法器的设计与实现OA
Design and implementation of FSATA multiplier
为了加快阵列乘法器的运算速度，降低延迟，提出了一种基于4选1多路选择器的乘法器设计方案。这种方案在每一步运算中同时处理两位操作数，使产生的部分积数量减少了一半，显著提高了乘法器的运算速度。FSATA乘法器采用VHDL语言进行编码，在Quartus上进行的仿真表明，相比于采用时序电路完成的设计，FSATA乘法器有更优的性能。
In order to improve the computing speed, reduce the delay of the array multiplier, a design based on four-to-one multiplexer was proposed. Two bits of the multiplier were executed on every step, so that the number of all partial products was reduced to half. Eventually, the FSATA multiplier was encoded by VHDL. The synthesis and simulation result in Quartus showed that the FSATA multiplier has a better performance.
商丽卫;刘耀军
太原科技大学计算机科学与技术学院,山西太原030024太原师范学院计算机科学与技术系,山西太原030012
计算机与自动化
阵列乘法器FSATA乘法器多路选择器VHDLQuartus
array multiplierFSATA multipliermultiplexerVHDLQuartus
《微型机与应用》 2012 (13)
87-89,92,4
基金项目：山西省重点学科专项基金项目（No：20101029）
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