半导体学报（英文版）2012，Vol.33Issue(9)：124-130,7.DOI:10.1088/1674-4926/33/9/095006
A novel high performance ESD power clamp circuit with a small area
A novel high performance ESD power clamp circuit with a small area
摘要
Abstract
A MOSFET-based electrostatic discharge (ESD) power clamp circuit with only a 10ns RC time constant for a 0.18-μm process is proposed.A diode-connected NMOSFET is used to maintain a long delay time and save area.The special structure overcomes other shortcomings in this clamp circuit.Under fast power-up events,the gate voltage of the clamp MOSFET does not rise as quickly as under ESD events,the special structure can keep the clamp MOSFET thoroughly off.Under a falsely triggered event,the special structure can turn off the clamp MOSFET in a short time.The clamp circuit can also reject the power supply noise effectively.Simulation results show that the clamp circuit avoids fast false triggering events such as a 30 ns/1.8 V power-up,maintains a 1.2 μs delay time and a 2.14 μs turn-offtime,and reduces to about 70％ of the RC time constant.It is believed that the proposed clamp circuit can be widely used in high-speed integrated circuits.关键词
electrostatic discharge/clamp circuit/false triggering/turn-off mechanismKey words
electrostatic discharge/clamp circuit/false triggering/turn-off mechanism引用本文复制引用
Yang Zhaonian,Liu Hongxia,Li Li,Zhuo Qingqing..A novel high performance ESD power clamp circuit with a small area[J].半导体学报（英文版）,2012,33(9):124-130,7.基金项目
Project supported by the National Natural Science Foundation of China (Nos.60976068,60936005) and the Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China (No.708083). （Nos.60976068,60936005）
