电子器件2012，Vol.35Issue(3)：317-321,5.DOI:10.3969/j.issn.1005-9490.2012.03.017
SOC中嵌入式存储器阴影逻辑的可测性设计
DFT for the Shadow Logic of Embedded Memory in SOC
施文龙 1林伟1
作者信息
- 1. 福州大学福建省微电子集成电路重点实验室,福州350002
- 折叠
摘要
Abstract
When the integrated circuits are tested by ATPG tools with the stuck-at model, the embedded memories in the integrated circuits design are taken as simple I/O models,ATPG tools fail to transfer the faults of combinational logics around the memories. Through the study of the DFT for SOC, the memory peripheral logics in a digital information security chip design were modified with the scanning principle. The design provided detectable paths for the shadow logics and improved the test coverage and fault coverage of the chip. The study analyzed the power and area and verified the effectiveness of the design.关键词
可测性设计/扫描设计/阴影逻辑/故障覆盖率/自动测试图形生成Key words
DFT/ scan design/ shadow logic/ fault coverage/ ATPG分类
信息技术与安全科学引用本文复制引用
施文龙,林伟..SOC中嵌入式存储器阴影逻辑的可测性设计[J].电子器件,2012,35(3):317-321,5.
