电子器件2012，Vol.35Issue(3)：331-333,3.DOI:10.3969/j.issn.1005-9490.2012.03.020
多相抽取滤波器的FPGA实现
The Realization of Polyphase Decimation Filter on FPGA
摘要
Abstract
Polyphase decomposition played an important role in multi-rate signals processing- The paper introduced the polyphase decomposition theory, combined with the polyphase decomposition form of the FIR decimation filter, realized 2 times polyphase structure decimation filter with Verilog HDL, simulated waveform by Quartus, verified the result and compared it with the theory value by MATLAB f which was correct. Finally, the programmable file was downloaded to FPGA. The design method of polyphase decimation filter was feasible; the entire design process was realized by software, easy to modify the parameter.关键词
抽取滤波器/多相分解/FPGA/Verilog HDLKey words
FIR filter/ FPGA/ Quartus II / Verilog HDL分类
信息技术与安全科学引用本文复制引用
谢海霞,孙志雄..多相抽取滤波器的FPGA实现[J].电子器件,2012,35(3):331-333,3.基金项目
海南省自然科学基金项目(611133) （611133）
三亚市院地科技合作项目(2010YD33) （2010YD33）
三亚市院地科技合作项目(2011YD03) （2011YD03）
