桂林电子科技大学学报2012，Vol.32Issue(4)：289-292,4.
低相噪频率合成器的设计与仿真
Simulation and design of low phase noise frequency synthesizer
摘要
Abstract
In order to obtain low phase noise and high integration level frequency source, The frequency synthesizer based on PLL was designed. Using RF simulation software ADS, lock time and phase noise were simulated to meet the expected value of the design. Hardware test was done by the VCO PLL chip ADF4360-7, locking frequency is 434 MHz, power is 1 dBm and phase noise is —87 dBc/Hz@10 kHz. It meets requirements of most measurement and communication system. The project can be promoted in RF circuit.关键词
频率合成/PLL/ADS/低相位噪声Key words
frequency synthesizeri PLL/ ADS/ low phase noise分类
信息技术与安全科学引用本文复制引用
贾海鹏,张向文..低相噪频率合成器的设计与仿真[J].桂林电子科技大学学报,2012,32(4):289-292,4.基金项目
国家自然科学基金(60804059) （60804059）
