华中科技大学学报：自然科学版2012，Vol.40Issue(7)：71-74,4.
快速锁定的宽频带CMOS锁相环设计
Design of a fast-lock CMOS phase-locked loop with wide band width
摘要
Abstract
A Fast-lock phase-locked loop（PLL）with a wide band width was designed based on CMOS process.By adding a bandwidth-control module,a wider bandwidth was used during transient to reduce lock time.While a phase lock was attained,the bandwidth was shifted to a smaller value for optimum spectrum.A wide-range voltage-controlled oscillator（VCO）was also designed in the circuit.The PLL can operate in the frequency range from 960to 2 560MHz with a setting time of less than 12 μs,and the power dissipation is from 8.9to 23.2mW at a 2.5Vsupply.关键词
锁相环/快速锁定/环形压控振荡器/宽频带/相位噪声Key words
phase-locked loop/fast lock/ring voltage-controlled oscillator/wide rage/phase noise分类
信息技术与安全科学引用本文复制引用
雷[金監]铭,何威,邹志革,温朝晔..快速锁定的宽频带CMOS锁相环设计[J].华中科技大学学报：自然科学版,2012,40(7):71-74,4.基金项目
湖北省自然科学基金资助项目 （）
华中科技大学自主创新基金资助项目 （）
