计算机工程2012，Vol.38Issue(16)：249-252,4.DOI:10.3969/j.issn.1000-3428.2012.16.065
高性能子字并行运算单元的设计与实现
Design and Implementation of High Performance Subword-Parallel Arithmetic Units
摘要
Abstract
A set of subword-parallel arithmetic units is implemented with a hardware shared method. With pipelined design, the proposed units can perform one 64-bit, two 32-bit, four 16-bit, eight 8-bit fixed-point operations, or one double-precision, two single-precision floating-point operations in single cycle. The arithmetic units are designed with Verilog HDL and implemented in 0.18μm standard CMOS process. The performance is evaluated by a real multimedia application based on Engineering and Scientific Computing Accelerator ESC A) system. Experimental results show that the subword-parallel arithmetic units have a good tradeoff between hardware cost and performance.关键词
多媒体技术/子字并行/硬件共享/运算单元/ESCA系统/协处理器Key words
multimedia technique/ subword parallel/ hardware sharing/ arithmetic units/ Engineering and Scientific Computing Accelerator (ESCA) system/ co-processor分类
信息技术与安全科学引用本文复制引用
董冕,吴丹,饶金理,黄威,戴葵,邹雪城..高性能子字并行运算单元的设计与实现[J].计算机工程,2012,38(16):249-252,4.基金项目
国家自然科学基金资助项目(NSFC 60976027,60973035) （NSFC 60976027,60973035）
湖北省自然科学基金资助项目(ZRZ0051,2010CDB02705) （ZRZ0051,2010CDB02705）
