计算机工程与科学2012，Vol.34Issue(7)：60-64,5.DOI:10.3969/j.issn.1007-130X.2012.07.011
一种基于块匹配算法的SAD运算加速器
A Block-Matching Algorithm Based Accelerator for SAD Computation
摘要
Abstract
Block-matching based motion estimation is one of the most important techniques in image and video applications. The sum of absolute difference (SAD) is the major computation in motion estimation and requires huge computation complexity and transmission bandwidth. This paper proposes a reconfigurable SAD accelerator, in which a 16 X 1 processing elements (PE) array and an adder tree structure are used to improve the execution speed of SAD computation. The pipeline partition of PE array and adder tree is performed carefully in order to increase the work frequency. In order to reduce the performance loss caused by data transfer delay, a DMA event mechanism is employed to transmit data when the SAD accelerator is working. The experimental results show that, the proposed architecture needs 4102 cycles for searching a 16X16 search window. With a 0. 13fxm CMOS standard cell technology, the proposed accelerator requires only 16. 8 k gates and 3. 5 KB of memory at the 750MHz operation frequency.关键词
运动估计/块匹配算法/处理单元阵列/视频编码Key words
motion estimation/BMA/processing element array/video coding分类
信息技术与安全科学引用本文复制引用
谷会涛,陈书明..一种基于块匹配算法的SAD运算加速器[J].计算机工程与科学,2012,34(7):60-64,5.基金项目
国家863计划资助项目(2009AA011704) （2009AA011704）
教育部“高性能微处理器技术”创新团队研究计划 （）
