现代电子技术2012，Vol.35Issue(14)：169-171,3.
基于FPGA的数字三相锁相环优化设计
Optimized design of digital three-phase-locked loop based on FPGA
胡海华1
作者信息
- 1. 成都航空职业技术学院电子工程系,四川成都610100
- 折叠
摘要
Abstract
Since there are many multiplication operations and trigonometric function operations in the digital three-phase-locked loop, which will occupy too much hardware resource, an optimized scheme of the digital three-phase-locked loop is proposed in this paper. The multiplication module reuse and CORDIC algorithm are adopted in the scheme to realize the trigonometric function operation. The digital three-phase-locked loops before and after optimization were decoded and implemented with Verilog HDL. The results of the simulation and the experiment verify the optimized digital three-phase-look loop can save the resource of FPGA, and lock the phase rapidly and accurately.关键词
FPGA/三相锁相环/乘法复用/CORDICKey words
FPGA/three-phase-locked loop/multiplication reuse/CORDIC分类
信息技术与安全科学引用本文复制引用
胡海华..基于FPGA的数字三相锁相环优化设计[J].现代电子技术,2012,35(14):169-171,3.
