电子学报2012，Vol.40Issue(8)：1665-1669,5.DOI:10.3969/j.issn.0372-2112.2012.08.027
基于缺陷均匀分布的集成电路制造成品率与可靠性之间的关系模型
A Relation Model Between Integrated Circuit Yield and Reliability Based on the Defect's Uniform Distribution
摘要
Abstract
In the study of IC design for manufacturing, models on the relationship of yield and reliability deserve much attention. The impact of defects on the yield and reliability is associated not only with the particle size of it but also with the location of it on the chip.In this paper, it is analyzed that the defects at the same size in interconnect different locations affect the effective width of interconnect wires, by discussing the impact of the loss of metal in the interconnect wire on the interconnect wire itself. The average effective width of interconnect wires is given based on the uniform distribution of defects. In addition, the model on the relationship of the IC manufacturing yield and reliability is presented based on the location of defects, by referring on the existing model of estimating yield and reliability. If the processing line is stable, the rate of the product failure can be estimated effectively by the expression and the yield of the processing line, which can shorten the development period of the new products.关键词
成品率/可靠性/缺陷/粒径分布Key words
yield/reliability/ defect/the size distribution of defect分类
信息技术与安全科学引用本文复制引用
赵天绪,段旭朝..基于缺陷均匀分布的集成电路制造成品率与可靠性之间的关系模型[J].电子学报,2012,40(8):1665-1669,5.基金项目
陕西省科技厅计划项目(No.SJ08-ZT13) （No.SJ08-ZT13）
