大连理工大学学报2012，Vol.52Issue(4)：594-598,5.
基于FPGA的WIMAXLDPC码译码器设计与实现
Design and implementation of WIMAX LDPC code decoder based on FPGA
摘要
Abstract
A partial parallel low density parity-check （LDPC） code decoder architecture based on turbo decoding message passing （TDMP）-normalized minimun sum （NMS） algorithm is proposed, which can not only achieve a convergence speed as high as TDMP algorithm, but also possess the easy-to-implement advantage of NMS algorithm while keeping a good bit error rate （BER） performance. The decoder supports the decoding of LDPC code of any code rate and code length defined in WIMAX standard. A barrel shifter-based shuffle network is designed which enables the decoder to support all the 19 code lengths. A dynamic iteration stopping criterion suitable for TDMF algorithm and its simplified version is employed with which the decoder can adjust the iteration number according to the decoding state adaptively. Experimental results show that the schemes proposed reduce the hardware cost as well as improve the throughput of the decoder effectively.关键词
WIMAX/低密度奇偶校验码译码器/现场可编程逻辑门阵列/TDMP/归一化最小和算法Key words
WIMAX/low density parity-check (LDPC) code decoder/field programmable gate array(FPGA)/TDMP/normalized minimum sum (NMS) algorithm分类
信息技术与安全科学引用本文复制引用
王秀敏,张洋,付娟,王尧..基于FPGA的WIMAXLDPC码译码器设计与实现[J].大连理工大学学报,2012,52(4):594-598,5.基金项目
国家质检总局科技计划资助项目 （）
浙江省科技计划优先主题重点_T业项目 （）
国家自然科学基金青年基金资助项目（200802025）. （）
