计算机工程2012，Vol.38Issue(19)：250-253,4.DOI:10.3969/j.issn.1000-3428.2012.19.064
基于65nm工艺的高性能低功耗处理器设计
Design of High Performance and Lower Power Processor Based on 65 nm Technology
摘要
Abstract
This paper presents the design of a high performance lower power RISC processor from architecture level, circuit level and backend design level. In architecture level, the processor is cache-free and register file extended to improve data locality and reduce memory accesses. In circuit level, gating clock technology is used to control MDU and register file to reduce power, and in backend level, this paper analyzes and compares GP and LP processes in TSMC 65 nm, and uses multi-threshold flow to increase speed and reduce power. Test results show that the processor can make throughput rate of RS forward error correction decoding increase 4 times~70 times, compared with other platforms.关键词
高性能低功耗处理器/扩展寄存器/门控时钟/65nm工艺/多阈值Key words
high performance and lower power processor/ extended register/ gating clock/ 65 nm technology/ multi-threshold分类
信息技术与安全科学引用本文复制引用
权衡,肖瑞瑾,欧鹏,尤凯迪,黄贝,虞志益..基于65nm工艺的高性能低功耗处理器设计[J].计算机工程,2012,38(19):250-253,4.基金项目
国家自然科学基金资助项目(61103008) （61103008）
国家科技重大专项基金资助项目(2011ZX03003-003-03) （2011ZX03003-003-03）
上海市科委集成电路专项基金资助项目(10706200300) （10706200300）
上海市青年科技启明星基金资助项目(11QA1400500) （11QA1400500）
