计算机工程与科学2012，Vol.34Issue(9)：71-76,6.DOI:10.3969/j.issn.1007-130X.2012.09.013
一种低成本128位高精度浮点SIMD乘加单元的设计与实现
Design and Implementation of a Low-Cost 128-bit Quadruple-Precision Floating-Point SIMD Fused Multiply-Add Unit
摘要
Abstract
Incorporating the SIMD unit has become one of the important ways to improve the performance of processors. The reused low-cost hardware design method for the fixed-point SIMD unit is mature,but it is not the case for the floating-point SIMD unit,which still remains the simple replication design method. To address the increasing computation demand for 128 — bit quadruple-precision floatingpoint operations, this paper proposes the hardware design of the low-cost 128-bit quadruple-precision floating-point SIMD fused multiply-add (FMA) unit. The experimental results show that the structure of the proposed FMA unit can be more optimized in performance and cost parameters in comparison to the traditional 128-bit quadruple-precision floating-point SIMD multiple-add unit.关键词
浮点乘加/单指令多数据/四精度Key words
floating-point fused multiply-add/SIMD/quadruple precision分类
信息技术与安全科学引用本文复制引用
黄立波,王志英,沈立,马胜..一种低成本128位高精度浮点SIMD乘加单元的设计与实现[J].计算机工程与科学,2012,34(9):71-76,6.基金项目
国家自然科学基金资助项目(60803041,60773024,61025009) （60803041,60773024,61025009）
国家973计划资助项目(2007CB310901) （2007CB310901）
