聊城大学学报：自然科学版2012，Vol.25Issue(3)：79-84,6.
基于FPGA的异步FIFO设计与实现
FPGA-based Design and Implementation of Asynchronous FIFO
摘要
Abstract
With the expanding of the density and scale of modern digital circuitry,a system will contain multiple clock.Therefore,the transfer of data between different clock becomes a serious problem needs to be solved.A reliable and feasible solution is asynchronous FIFO.Asynchronous FIFO require very strict clock technology,it is difficult to make the correct design of synthesis and analysis.This paper presents a design method of asynchronous FIFO which based on read/write counter in terms of gray code.This method effectively avoid the metastable state in the data transmission between different clock and given a comprehensive simulation results.关键词
多时钟/异步fifo/verilog/HDL/格雷码Key words
multi-asynchronous/asynchronous fifo/verilog HDL/gray code分类
信息技术与安全科学引用本文复制引用
王伟国,张振东..基于FPGA的异步FIFO设计与实现[J].聊城大学学报：自然科学版,2012,25(3):79-84,6.基金项目
中国科学院长春光学精密机械与物理研究所三期创新工程资助项目 （）
