四川理工学院学报：自然科学版2012，Vol.25Issue(5)：50-53,4.
一种基于多级流水线加法器的累加电路设计研究
Research on a Kind of Accumulator Basing on Multilevel Pipeline Adder
袁松 1唐敬友 2刘莉1
作者信息
- 1. 西南科技大学 理学院
- 2. 西南科技大学国防学院,四川绵阳621010
- 折叠
摘要
Abstract
Purpose-designed circuits can accelerate the speed of scientific calculation. Multiple data accumulation is a common operation in scientific calculation. It is easy to meet pipeline data hazards during designing the hardware accumula- tor. Our design is dividing those data into two kinds of modules according to pipeline level, and different modules using dif- ferent accumulation methods. Based on a multilevel pipeline adder, this design is implemented on a FPGA. It has less hard- ware resources and higher pipeline utilization, and the control is relatively simple. Especially for large-scale data, its advan- tages can be fully taken on.关键词
硬件加速/FPGA/多级流水线/累加器Key words
hardware acceleration/FPGA/multilevel pipeline/accumulator分类
信息技术与安全科学引用本文复制引用
袁松,唐敬友,刘莉..一种基于多级流水线加法器的累加电路设计研究[J].四川理工学院学报：自然科学版,2012,25(5):50-53,4.
