火力与指挥控制2012，Vol.37Issue(11)：170-172,3.
基于FPGA的抽取滤波器的实现
Implementation of Decimation Filter Based on FPGA
拜哲峰 1王永治 1白利军 1岳存勇1
作者信息
- 1. 北方自动控制技术研究所,太原030006
- 折叠
摘要
Abstract
This article discusses the decimation filter frequency characteristics of the structure and proposes an efficient decimation filter - cascaded integrator comb filter. It is a linear phase FIR filter, by working at high sampling rate of cascaded ideal integrator and the low sampling rate of the cascade differentiator formed, according to anti-aliasing and anti-mirror indicators to determine the number of required cascade N then, the use of FPGA design methods, functional simulation and waveform are simulated to verify the correctness of decimation filter.关键词
抽取滤波器/级联积分/FPGAKey words
decimation filter/cascaded integrator /FPGA分类
信息技术与安全科学引用本文复制引用
拜哲峰,王永治,白利军,岳存勇..基于FPGA的抽取滤波器的实现[J].火力与指挥控制,2012,37(11):170-172,3.
