计算机工程2012，Vol.38Issue(23)：255-258,4.DOI:10.3969/j.issn.1000-3428.2012.23.063
高性能并行Turbo译码器的VLSI设计
VLSI Design of High Performance Parallel Turbo Decoder
摘要
Abstract
This paper presents a highly-parallel Turbo decoder architecture. It utilizes 32-parallel radix-4 component decoders and its throughput is increased by 43.2% at most with modified sliding window and memory partition scheme. The proposed decoder is implemented in SMIC 0.13 nm technology, which has 1.94 M equivalent gate counts and achieves 1.19 Gb/s running at 294 MHz with 5.5 iterations. It meets the peak data rate requirement of 4G mobile communication standard LTE-Advanced.关键词
Turbo码/译码器/并行结构/基-4/4G移动通信Key words
Turbo code/ decoder/ parallel architecture/ radix-4/ 4G mobile communication分类
信息技术与安全科学引用本文复制引用
陈绪斌,曹嘉麟,陈赟,曾晓洋..高性能并行Turbo译码器的VLSI设计[J].计算机工程,2012,38(23):255-258,4.基金项目
国家"863"计划基金资助项目(SQ2008AA01ZX1480432) （SQ2008AA01ZX1480432）
国家科技重大专项基金资助项目"新一代宽带无线移动通讯网"(2011ZX03003-003-03) （2011ZX03003-003-03）
