摘要
Abstract
In this paper, a finite state machine based on incremental photoelectrical encoder interface circuit design is proposed. In a photoelectric encoder pulse cycle,the design of state machine is realized using hardware description language, through the A, B two signal level changes were subdivided. And the feasibility of this design is verified in the software Qtiartus Ⅱ environment to compile and simulate.关键词
增量式光电编码器/有限状态机/硬件描述语言/FPGAKey words
incremental photoelectrical encoder/ finite state machine/ hardware description language/ FPGA分类
信息技术与安全科学
