半导体学报（英文版）2012，Vol.33Issue(11)：110-114,5.DOI:10.1088/1674-4926/33/11/115010
A digital background calibration algorithm of a pipeline ADC based on output code calculation
A digital background calibration algorithm of a pipeline ADC based on output code calculation
Shao Jianjian 1Li Weitao 1Sun Cao 1Li Fule 1Zhang Chun 1Wang Zhihua1
作者信息
- 1. Institute of Microelectronics, Tsinghua University, Beijing 100084, China
- 折叠
摘要
Abstract
This paper proposes a digital background calibration algorithm to correct linearity errors in a pipelined analog-to-digital converter (ADC).The algorithm does not modify the analog circuit of pipelined stages and calibrates the raw conversion output by using a backend digital logic.Based on the analysis of the output codes,the calibration logic estimates the bit weight of each stage and corrects the outputs.An experimental 14-bit pipelined ADC is fabricated to verify the algorithm.The results show that INL errors drop from 20 LSB to 1.7 LSB,DNL errors drop from 2 LSB to 0.4 LSB,SNDR grows from 57 to 65.7 dB and THD drops from 58 to-81 dB.The linearity of the pipelined ADC is improved significantly.关键词
pipeline/ ADC/ output code calculation/ background calibrationKey words
pipeline/ ADC/ output code calculation/ background calibration引用本文复制引用
Shao Jianjian,Li Weitao,Sun Cao,Li Fule,Zhang Chun,Wang Zhihua..A digital background calibration algorithm of a pipeline ADC based on output code calculation[J].半导体学报（英文版）,2012,33(11):110-114,5.
