半导体学报（英文版）2012，Vol.33Issue(11)：115-120,6.DOI:10.1088/1674-4926/33/11/115011
Design and implementation of an ultra-low power passive UHF RFID tag
Design and implementation of an ultra-low power passive UHF RFID tag
摘要
Abstract
This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol.The tag chip includes an RF/analog front-end,a baseband processor,and a 512-bit EEPROM memory.To improve power conversion efficiency,a Schottky barrier diode based rectifier is adopted.A novel voltage reference using the peaking current source is discussed in detail,which can meet the low-power,low-voltage requirement while retaining circuit simplicity.Most of the analog blocks are designed to work under sub-1 V to reduce power consumption,and several practical methods are used to further reduce the power consumption of the baseband processor.The whole tag chip is implemented in a TSMC 0.18 μm CMOS process with a die size of 800 × 800 μm2.Measurement results show that the total power consumption of the tag chip is only 7.4 μW with a sensitivity of -12 dBm.关键词
UHF RFID tag/ voltage reference/ demodulator/ low powerKey words
UHF RFID tag/ voltage reference/ demodulator/ low power引用本文复制引用
Shen Jinpeng,Wang Xin'an,Liu Shan,Zong Hongqiang,Huang Jinfeng,Yang Xin,Feng Xiaoxing,Ge Binjie..Design and implementation of an ultra-low power passive UHF RFID tag[J].半导体学报（英文版）,2012,33(11):115-120,6.基金项目
Project supported by the Shenzhen Key Laboratory Development Project,China (No.CXB201104210007A). （No.CXB201104210007A）
