半导体学报（英文版）2012，Vol.33Issue(11)：126-133,8.DOI:10.1088/1674-4926/33/11/115013
A 1.8 V low-power 14-bit 20 Msps ADC with 11.2 ENOB
A 1.8 V low-power 14-bit 20 Msps ADC with 11.2 ENOB
Cai Hua1
作者信息
- 1. State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China
- 折叠
摘要
Abstract
This paper describes the design of a 14-bit 20 Msps analog-to-digital converter (ADC),implemented in 0.18 μm CMOS technology,achieving 11.2 effective number of bits at Nyquist rate.An improved SHA-less structure and op-amp sharing technique is adopted to significantly reduce the power.The proposed ADC consumes only 166 mW under 1.8 V supply.A fast background calibration is utilized to ensure the overall ADC linearity.关键词
CMOS/ opamp-sharing/ low-power and background calibrationKey words
CMOS/ opamp-sharing/ low-power and background calibration引用本文复制引用
Cai Hua..A 1.8 V low-power 14-bit 20 Msps ADC with 11.2 ENOB[J].半导体学报（英文版）,2012,33(11):126-133,8.
