半导体学报（英文版）2012，Vol.33Issue(12)：73-80,8.DOI:10.1088/1674-4926/33/12/125005
Design and analysis of a bang-bang PLL for 6.25 Gbps SerDes
Design and analysis of a bang-bang PLL for 6.25 Gbps SerDes
摘要
Abstract
An analysis illustrates the loop nonlinear performance in a bang-bang PLL.A third-order equivalent model is deduced to give an approximate evaluation of the loop parameters.The architecture of the proposed phase detector is composed of four master-slave DFFs and two XORs based on the current mode logic circuit.A no-load architecture is introduced in the XOR design.The oscillator is designed with an LC VCO implementation for the jitter requirement.A simple voltage-to-current converter is proposed to drive the loop filter.The loop filter design is described in detail,which is important to ensure the nonlinear loop stability.The chip is fabricated in a 0.18μm CMOS technology.The experimental results show that it can achieve the frequency range of 2.995 to 3.35 GHz,and a phase noise of-118.38 dBc/Hz at 1 MHz offset.The frequency to voltage gain is 270 MHz/V.The chip consumes less than 81 mW with 1.8 V supply voltage,and it occupies a 0.5 mm2 area.关键词
PLL/ bang-bang PD/ LC VCOKey words
PLL/ bang-bang PD/ LC VCO引用本文复制引用
Zhou Mingzhu..Design and analysis of a bang-bang PLL for 6.25 Gbps SerDes[J].半导体学报（英文版）,2012,33(12):73-80,8.基金项目
Project supported by the Zhejiang Provincial Natural Science Foundation of China (No.Y1110991),the National Natural Science Foundation of China (No.61102027),and the Start Research Foundation of Hangzhou Dianzi University (No.KYS045609050). （No.Y1110991）
