首页|期刊导航|半导体学报（英文版）|A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp
半导体学报（英文版）2013，Vol.34Issue(1)：53-57,5.DOI:10.1088/1674-4926/34/1/014007
A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp
A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp
摘要
Abstract
The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD (electro-static discharge) clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.关键词
ESD protection/ESD robustness/SCR-LDMOS/latch-up/holding voltageKey words
ESD protection/ESD robustness/SCR-LDMOS/latch-up/holding voltage引用本文复制引用
Pan Hongwei,Liu Siyang,Sun Weifeng..A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp[J].半导体学报（英文版）,2013,34(1):53-57,5.基金项目
Project supported by the Natural Science Foundation of Jiangsu Province (No.BK2011059) and the Program for New Century Excellent Talent in University (No.NCET-10-0331). （No.BK2011059）
