电子器件2012，Vol.35Issue(6)：657-660,4.DOI:10.3969/j.issn.1005-9490.2012.06.008
基于FPGA的CRC编解码器实现
Implementation of CRC Encoder and Decoder Based on FPGA
摘要
Abstract
The Cyclic Redundancy Check (CRC) is a widely used error control method in communicating fields to improve the reliability for data transmission. This paper introduces the principle of CRC code and the ideas on designing CRC encoder and decoder. After designing and simulating the CRC(7 ,3) with VHDL language on Quartus II , the programming data files are downloaded to implement the design of CRC (7,3) encoder and decoder with FPGA chip at the last. The simulation and experiment results show that using this method the CRC encoder and decoder with fast speed,high reliability and easy large scale integration advantages are achieved.关键词
CRC/编码器/解码器/FPGA/VHDLKey words
CRC/ encoder/ decoder/ FPGA/ VHDL分类
信息技术与安全科学引用本文复制引用
孙志雄,谢海霞..基于FPGA的CRC编解码器实现[J].电子器件,2012,35(6):657-660,4.基金项目
海南省自然科学基金项目(611133) （611133）
三亚市院地科技合作项目(2010YD33) （2010YD33）
三亚市院地科技合作项目(2011YD03) （2011YD03）
琼州学院校级青年科学基金项目(QYQN201242) （QYQN201242）
